>tar zxvf Verilog2C++.tgz >cd Verilog2C++ >make >make install >cd .. |
Verilog2C++ file_name module_name
[posedge port_name]
[negedge port_name]
[comments]
[dumpvars]
|
>tar zxvf Sample.tgz >cd Sample |
>Verilog2C++ UDIV64.v2k UDIV64 posedge CLK negedge RSTn |
>g++ -O3 bench.cc UDIV64.cc -o simc >./simc |
>v2v UDIV64.v2k > UDIV64.v >iverilog bench.v UDIV64.v -o simv >./simv |
>vcs +2state +v2k bench.v UDIV64.v2k >./simv |
>Verilog2C++ UDIV64.v2k UDIV64 posedge CLK negedge RSTn dumpvars >g++ -O3 bench_dump.cc UDIV64.cc -o simc >./simc |
>gtkwave dump.vcd UDIV64.tr |