/*
 * Copyright (c) 2002 moe
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
 *    General Public License as published by the Free Software
 *    Foundation; either version 2 of the License, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
// unsigned 64bit divider

module UDIV64
  (
   input  [63:0] A,
   input  [63:0] B,
   input         EN,
   //
   output [63:0] UDIV,
   output reg    BUSY,
   //
   input         CLK,
   input  	 RSTn
   );
  ////////////////////////////////////////////////////////////////////////

  reg [5:0] 	     i;
  always @( posedge CLK or negedge RSTn )
    if( !RSTn )
      begin
	BUSY <=0;
	i    <=0;
      end
    else
      if( EN )
	begin
	  BUSY <=1;
	  i    <=63;
	end
      else if( BUSY )
	{BUSY,i} <={BUSY,i}-1;
  
  reg [63:0] 	     h;
  reg [63:0] 	     l;  
  always @( posedge CLK )
    if( EN )
      begin
	h <=A>>63;
	l <=A<<1;
      end
    else if( BUSY )
      begin
	if( h>=B )
	  begin
	    h <=((h-B)<<1)|(l>>63);
            l <=(l<<1)|1;
	  end
	else
	  begin
            h <=(h<<1)|(l>>63);
            l <=l<<1;
	  end
      end
  
  assign 	     UDIV =l;   
endmodule // UDIV64