/*
 * Copyright (c) 2002 moe
 *
 *    This source code is free software; you can redistribute it
 *    and/or modify it in source code form under the terms of the GNU
 *    General Public License as published by the Free Software
 *    Foundation; either version 2 of the License, or (at your option)
 *    any later version.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *    GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
 */
// UDIV64 test bench
// Verilog version

module bench;

  ////////////////////////////////////////////////////////////////////////
  reg [63:0] A;
  reg [63:0] B;
  reg 	     EN;
  //
  wire [63:0] UDIV;
  wire 	      BUSY;
  //
  reg 	      CLK;
  reg 	      RSTn;
  //
  UDIV64 udiv64
    (
     A,
     B,
     EN,
     
     UDIV,
     BUSY,
     
     CLK,
     RSTn
   );
  ////////////////////////////////////////////////////////////////////////

  ////////////////////////////////////////////////////////////////////////
  initial
    CLK =0;
  always
    CLK =#5 ~CLK;
  ////////////////////////////////////////////////////////////////////////

  ////////////////////////////////////////////////////////////////////////
  integer     ai,bi,i;
  reg [63:0]  ref_UDIV;
  reg [63:0]  am,bm;
  //
  initial
    begin
      RSTn =1;
      @( negedge CLK );
      RSTn =0;
      A =0;
      B =0;
      EN =0;
      @( negedge CLK );
      RSTn =1;
      @( negedge CLK );
      
      for( ai=0;ai<=64;ai=ai+1 )
	begin
	  if( ai==64 )
	    am =0;
	  else
	    am =(~64'h0)>>(63-ai);

	  for( bi=0;bi<64;bi=bi+1 )
	    begin
	      bm =(~64'h0)>>(63-bi);
	      
	      for( i=0;i<10000;i=i+1 )
		begin
		  A[15: 0] =$random();
		  A[31:16] =$random();
		  A[47:32] =$random();
		  A[63:48] =$random();
		  A =A|(1<<ai);
		  A =A&am;
		  
		  B[15: 0] =$random();
		  B[31:16] =$random();
		  B[47:32] =$random();
		  B[63:48] =$random();
		  B =B|(1<<bi);
		  B =B&bm;
		  
		  EN =1;
		  @( negedge CLK );
		  EN =0;
		  while( BUSY )
		    @( negedge CLK );
		  
		  ref_UDIV =A/B;
		  if( ref_UDIV!==UDIV )
		    begin
		      $write("%X / %X = %X != %X\n",A,B,ref_UDIV,UDIV);
		      $write("fail!\n");
		      $finish;
		    end
		end
	    end
	end
      
      $write("pass!\n");
      $finish;
    end
  ////////////////////////////////////////////////////////////////////////
endmodule // bench