Verilog2C++ is a Verilog to C++ translation program.

  1. Introduction
    Verilog2C++ translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions.

  2. Verilog2C++ charcteristics
    • Support for IEEE1364-2001
    • Only two sate simulation
    • Static scheduled and cycle based simulation
    • Not include the simulation kernel
    • Not support system tasks
    • Not support initial and task statement

  3. Install
    Download a "Verilog2C++.tgz"
    >tar zxvf Verilog2C++.tgz
    >cd Verilog2C++
    >make install
    >cd ..

  4. Synopsis
    Verilog2C++ file_name module_name [posedge port_name] [negedge port_name] [comments] [dumpvars]
    • file_name : Verilog source
    • module_name : Top level module
    • port_name : Synchronous port

  5. Example
    Download a "Sample.tgz"
    >tar zxvf Sample.tgz
    >cd Sample
    This is a RTL implementation of unsigned 64 bit divider.
    "UDIV64.v2k" is written in Verilog-2001 as module UDIV64.

    >Verilog2C++ UDIV64.v2k UDIV64 posedge CLK negedge RSTn
    It is then translated to C++ using Verilog2C++ to give "UDIV64.hh" and "" .

    A C++ test bench "" is created manually from a Verilog test bench "bench.v" .
    >g++ -O3 -o simc

    If you have a Icarus Verilog.
    >v2v UDIV64.v2k > UDIV64.v
    >iverilog bench.v UDIV64.v -o simv

    If you have a VCS.
    >vcs +2state +v2k bench.v UDIV64.v2k

    If you want to dump a VCD file.
    >Verilog2C++ UDIV64.v2k UDIV64 posedge CLK negedge RSTn dumpvars
    >g++ -O3 -o simc

    If you have a GTKWave.
    >gtkwave dump.vcd

  6. Technology overview

  7. Benchmark

  8. To do
    I am planning to add these features for next version.
    • Support for SystemVerilog
    • SystemC and CycleC wapper

  9. System requirements
    Verilog2C++ is written in C++ without any specific libraries and tools. But, only tested on my system.
    I have developped Verilog2C++ on tools shown below.
    • linux 2.4.18 on x86
    • gcc 3.2 20020903
    • bison 1.35
    • flex 2.5.4
    • glibc 2.2.93
    • libstdc++ 3.2 20020826

  10. Download

  11. Resources
    Icarus Verilog is a GPLed simulation and synthesis tool
    Verilator is a Verilog to C translator
    GTKWave is electronic waveform viewer

  12. Messages and comments Logo